Design Verification Engineer

Austin, Texas, United States

SNAPSHOT

  • Full-Time
  • 1
  • Sometimes
  • 5-7 years
  • US Citizen

Job Description

Responsibilities -

Responsible for functional verification of mixed-signal audio CODECs. Detailed responsibilities include but are not limited to:

verification planning

testbench development

failure analysis and resolution

coverage analysis and population

digital/mixed-signal modeling

directed/constraint-random test generation

flow development.

Candidates must work closely with digital/analog designers, applications engineers and manufacturing test to support both pre-silicon verification and post silicon validation efforts.

Skills/Experience -

Requires a MSEE/MSCS and 5 years of verification experience preferably in mixed signal products.

Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/OVM, UVM, AVM, Vera, e)

The candidate must have solid scripting skills with Matlab, Perl, Unix/Linux shell, TCL, and must be able to write and debug analog behavioral models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing and Verilog Assertions are also a plus. The proven ability to create, evaluate, debug, and improve a verification process is essential for this position.

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